Ensure Stable Operation with the Reset Release IP for Intel Stratix 10 & Agilex FPGAs

Ensure Stable Operation with the Reset Release IP for Intel Stratix 10 & Agilex FPGAs

Table of Contents

• Background
• Design Implications
• Instantiating the Reset Release IP
• Conclusion
• Resources
• FAQ

Background

The Stratix 10 and Agilex FPGAs from Intel are configured through the Secure Device Manager (SDM), which provides a secure and fully authenticated configuration scheme. This configuration process involves the SDM sending configuration data to each sector in the FPGA. However, due to the asynchronous configuration of sectors, different areas of the sectors may enter user mode before the entire sector is fully configured. This can result in the intended initial state of the design becoming a transitory state. Reset logic becomes crucial in ensuring the correct operation of state machines and avoiding illegal or unknown states.

Design Implications

Without adequate reset mechanisms, the state machines in a design can begin operating when only a portion of the FPGA Fabric is active, while neighboring logic remains frozen. This can lead to unpredictable behavior and incorrect operation. To prevent this, the Reset Release IP is used to hold the circuit in reset until the entire fabric has entered user mode. It ensures that the design starts from a known and stable state, preventing issues caused by partially configured sectors.

Designs that use PLLs for clocking also require careful consideration of the reset sequence. To avoid potential issues with PLL locking, the Reset Release IP can be used to control resets based on the initialization status of the PLL. This ensures that the design remains in a reset state until the PLL is locked, providing a reliable and stable clock source.

Additionally, initializing registers with proper initial conditions is essential for correct design operation. While software tools can assign an initial condition of zero to registers, it is recommended to rely on the reset network to maintain the desired initial condition. This is especially important due to the configuration process in Stratix 10 and Agilex devices, where relying on initial conditions of registers may not be reliable. Instead, proper reset signals should be used to ensure a consistent and controlled start-up of the design.

Instantiating the Reset Release IP

To instantiate the Reset Release IP, you can locate it in the IP catalog and go through the process of creating your IP. You can select whether the interface will be a reset interface or a conduit interface, depending on your design requirements. The instantiation of the Reset Release IP can be achieved by following the provided shell codes, which are available in both VHDL and Verilog.

When instantiating the Reset Release IP, the configuration can vary depending on the specific design requirements. For example, the Reset Release IP can be used to hold the PLL and the entire design in reset until the FPGA is fully configured. Alternatively, an input reset can be used to reset both the PLL and the design running in the FPGA. The specific configuration will depend on the desired behavior and operation of the design.

Conclusion

The Reset Release IP is an essential component in Intel Stratix 10 and Agilex designs, ensuring a controlled and reliable start-up of the FPGA fabric. By properly managing the reset signals and preventing transitory states, the Reset Release IP helps guarantee the correct operation of state machines and avoid illegal or unknown states. Its simple instantiation process allows designers to easily incorporate it into their designs and achieve a predictable and stable system behavior.

Resources

• Intel Stratix 10 Documentation
• Intel Agilex Documentation

FAQ

Q: What is the purpose of the Reset Release IP? A: The Reset Release IP ensures that the FPGA fabric starts from a known and stable state by holding the circuit in reset until the entire fabric has entered user mode. It prevents issues caused by partially configured sectors.

Q: Why is proper initialization of registers important? A: Proper initialization of registers ensures a correct start-up of the design. Relying on the reset network and avoiding reliance on initial register conditions is recommended due to the nature of the configuration process in Intel Stratix 10 and Agilex devices.

Q: Can the Reset Release IP be used with PLLs? A: Yes, the Reset Release IP can be used in conjunction with PLLs. It can control the reset sequence based on the initialization status of the PLL, ensuring a stable clock source.

Q: Is the Reset Release IP easy to instantiate? A: Yes, the Reset Release IP can be easily instantiated through the IP catalog. The provided shell codes in VHDL and Verilog make the instantiation process straightforward.

Q: Where can I find more information about Intel Stratix 10 and Agilex FPGAs? A: You can refer to the official Intel documentation for more information about the Stratix 10 and Agilex FPGAs. The provided resources section contains links to the respective documentation pages.