Exploring Shared Virtual Addressing in KVM

Exploring Shared Virtual Addressing in KVM

Table of Contents:

1. Introduction
2. Shared Virtual Addressing in KVM 2.1 What is Shared Virtual Addressing? 2.2 Benefits of Shared Virtual Addressing
3. Implementation of Address Translation in KVM 3.1 CPU Page Tables vs IMU Page Tables 3.2 First-Level and Second-Level Translation
4. Nested Translation in KVM 4.1 Introduction to Nested Translation 4.2 Achieving GPA to GPA and GPA to HV Translation
5. Enabling Shared Virtual Memory in KVM 5.1 Requirements for Virtual IMU 5.2 Caching Mode and Its Role in Translation Structure Modifications 5.3 Handling Page Faults during Translation 5.4 Communication between Host and Guest 5.5 API and Interface Updates
6. Upstream Status and Interdependencies 6.1 Native SVA vs Virtualized SVA 6.2 Comparing VTD and SMU Implementations 6.3 Shared Components and Individual Components
7. Conclusion
8. Frequently Asked Questions (FAQs)

Introduction Shared Virtual Addressing is a concept in KVM (Kernel-based Virtual Machine) that allows for the sharing of address space between a device and a processor. This article explores the implementation of shared virtual addressing in KVM, focusing on the benefits, address translation, nested translation, enabling shared virtual memory, upstream status, and interdependencies.

Shared Virtual Addressing in KVM Shared Virtual Addressing (SVA) in KVM refers to the shared address space between a device and a processor. It simplifies the programming model and enhances efficiency in workload submission. By utilizing CPU page tables, KVM achieves a unified address space view for both the device and processor.

Implementation of Address Translation in KVM In KVM, address translation is implemented using CPU page tables instead of IMU (Intel Memory Management Unit) page tables. This allows for a shared address space between the CPU and the device. The implementation involves first-level and second-level translation, which are used for GPA to GPA translation and GPA to HV translation.

Nested Translation in KVM Nested translation in KVM enables achieving GPA to GPA and GPA to HV translation. By using first-level and second-level translation, KVM implements shared virtual memory. This allows for a more efficient and simplified programming model in the virtual machine.

Enabling Shared Virtual Memory in KVM Enabling shared virtual memory in KVM requires a virtual IMU with the necessary capabilities. Caching mode plays a crucial role in translation structure modifications. It requires caching invalidation for any changes made on the translation structure. Additionally, handling page faults during translation, communication between the host and guest, and API and interface updates are essential aspects of enabling shared virtual memory in KVM.

Upstream Status and Interdependencies The upstream status of shared virtual addressing in KVM involves both native and virtualized SVA. The implementations by VTD and SMU differ in terms of address allocation, page requests, and private data. The components of this implementation have shared and individual aspects, contributing to the overall success of shared virtual addressing in KVM.

Conclusion Shared virtual addressing in KVM provides a convenient and efficient way to submit workloads to accelerators. It simplifies the programming model and enhances efficiency. The implementation involves various aspects such as address translation, nested translation, enabling shared virtual memory, and dealing with upstream status and interdependencies.

Frequently Asked Questions (FAQs) Q1. Are there plans to add cards with support for the PCIe web interface? Q2. Can the CM bit be eliminated and updates sent only during invalidation of page table entries? Q3. Is the page request interface standardized in PCI Express? Q4. Is caching mode the only choice for translation structure modifications? Q5. What are the requirements for enabling virtual IOMMU? Q6. How are page faults handled during translation in KVM? Q7. What is the communication mechanism between the host and guest in shared virtual addressing? Q8. What are the API and interface updates in KVM for enabling shared virtual memory?

Highlights

• Shared virtual addressing allows for the sharing of address space between a device and a processor in KVM.
• KVM uses CPU page tables instead of IMU page tables for address translation.
• Nested translation in KVM enables achieving GPA to GPA and GPA to HV translation.
• Enabling shared virtual memory in KVM requires a virtual IMU with the necessary capabilities.
• The upstream status of shared virtual addressing in KVM involves both native and virtualized SVA.
• FAQs address common concerns related to PCIe web interface support, caching mode, page faults, and communication between host and guest.