Arria 10 FPGA & SoC: Réinventer la gamme mi-haute

Table of Contents

1. Introduction
2. What is the reinvention of the mid-range FPGA and SOCs?
3. The breakthrough capabilities of Ariya-10 FPGAs and SOCs
   • 3.1 Performance improvement
   • 3.2 Increased I/O bandwidth
4. Power optimization in mid-range devices
   • 4.1 Integrated ARM processor and memory controllers
   • 4.2 Power reduction technologies
5. Software tools for FPGA design
   • 5.1 Quartus II software design suite
   • 5.2 Qsys system integration tool
   • 5.3 OpenCL and C-based design entry tools
6. Specific applications driving the need for reinvention
   • 6.1 Telecommunications industry
   • 6.2 Storage market and cloud computing
   • 6.3 Broadcast television and 4K Ultra HD
   • 6.4 Military applications and signal bandwidth
7. Quantifying the performance and power requirements of these applications
8. The path to the new definition of mid-range FPGAs and SOCs
9. Conclusion
10. References

🚀 The Reinvention of Mid-Range FPGAs and SOCs: Unlocking Breakthrough Capabilities

The demand for information across various devices has witnessed an exponential surge in recent times. From computers to tablets, smartphones, TVs, and even military equipment, data transmission is increasing at an unprecedented pace. As a result, the wireline and wireless infrastructure within the telecommunications industry is burdened by a massive explosion of data. Altera Corporation, acknowledged as a technology leader, has responded to this challenge with the reinvention of mid-range Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SOCs) – an innovation aptly named the Ariya-10 FPGA and SOC.

🔍 What is the Reinvention of the Mid-Range FPGA and SOC?

To meet the growing demands for higher performance while optimizing costs and power, Altera embarked on reimagining the mid-range category. At its core, this reinvention incorporated a meticulous selection of the 20-nanometer SOC process technology, in collaboration with its partner TSMC. The incorporation of a high-performance Fabric architecture within the FPGA paved the way for delivering unparalleled performance.

3.1 Performance Improvement

The integration of the 20-nanometer SOC process and high-performance fabric architecture within the Ariya-10 FPGAs and SOCs enables a remarkable 15% higher performance compared to previous generation high-end FPGAs. Furthermore, there is a staggering 60% higher performance compared to previous generation mid-range FPGAs. This performance boost sets a new benchmark in the mid-range class of FPGAs.

3.2 Increased I/O Bandwidth

The need for mid-range devices to deliver terabit-level I/O bandwidth is being addressed through the integration of 96 high-speed serial transceivers. These transceivers have a impressive capability of supporting up to 28 gigabits per Second, yielding a bandwidth of over 3.6 terabits per second. Furthermore, the high-speed transceivers permit the connection of up to 16 serial memory interfaces or four links at data rates up to 15 gigabits per second, providing a bandwidth of 1 terabit per second in hybrid memory cubes. The I/O structures are also enhanced to facilitate direct connection with high-performance external memory interfaces, such as DDR4 SDRAM.

⚙️ Power Optimization in Mid-Range Devices

The reinvention of mid-range FPGAs and SOCs not only emphasizes performance improvements but also addresses power optimization. Altera has effectively integrated a dual-core ARM processor, hard memory controllers, and increased RAM capacity into the products, totaling over 1 million logic elements. This exceptional level of integration significantly reduces chip count, resulting in reduced power consumption and cost while maximizing chip designer productivity.

4.1 Integrated ARM Processor and Memory Controllers

The integration of a dual-core ARM processor and memory controllers adds a whole new dimension to the capabilities of mid-range devices. This enables the seamless integration of various logic elements into a single system-level chip, minimizing the quantity of chips required on a board, and achieving significant power and cost savings without compromising productivity.

4.2 Power Reduction Technologies

In addition to the power savings achieved through the choice of the 20-nanometer SOC process and integrated hard IP, Altera has introduced a comprehensive set of power reduction technologies. These technologies can provide up to a remarkable 40% lower power consumption in comparison to previous generation mid-range FPGAs. The innovative power savings make the reinvented mid-range FPGAs and SOCs even more attractive for power-sensitive applications.

💻 Software Tools for FPGA Design

Altera's rich history of software leadership is continued with the introduction of advanced tools that enhance the productivity of FPGA designers. The Ariya-10 FPGAs and SOCs are fully integrated into the Quartus II software design suite, known for providing the fastest compile times in the industry. The suite includes the Qsys system integration tool, OpenCL, C-based design entry tools, and DSP Builder. Each of these tools plays a crucial role in saving significant time and effort during the FPGA design process.

5.1 Quartus II Software Design Suite

The Quartus II software design suite is a comprehensive platform that offers a wide array of features for FPGA design. With its fast compile times and exceptional performance, it simplifies the development process by reducing turnaround time and improving the overall productivity of designers.

5.2 Qsys System Integration Tool

The Qsys system integration tool facilitates the creation and integration of custom FPGA components, ensuring seamless connectivity and compatibility between these components. Its user-friendly interface and design workflow make complex system designs more manageable, further streamlining the design process.

5.3 OpenCL and C-based Design Entry Tools

OpenCL, the C-based design entry tool, allows designers to harness the power of a high-level programming language to create FPGA designs. It simplifies the design process by enabling programmers to leverage their programming skills without extensive hardware expertise. The C-based design entry tools provide an efficient and straightforward approach for creating FPGA designs.

📊 Specific Applications Driving the Need for Reinvention

The driving force behind the reinvention of mid-range FPGAs and SOCs is the increasing demand from specific industries and applications. Let's explore the sectors where the Ariya-10 FPGAs and SOCs display their breakthrough capabilities.

6.1 Telecommunications Industry

As the demand for wireless infrastructure, 100-gigabit, and 200-gigabit networking, and data transmission continues to grow, the telecommunication industry faces immense challenges. The Ariya-10 FPGAs and SOCs offer unparalleled performance improvements, ensuring telecommunications providers can keep up with the ever-increasing demand while maintaining cost and power efficiency.

6.2 Storage Market and Cloud Computing

With the rise of cloud computing, the storage market is under immense pressure to accommodate the growing requirements of flash-assisted storage systems. The reinvented mid-range FPGAs and SOCs deliver the necessary performance and bandwidth to meet the demands of cloud computing, offering a viable and powerful solution in this cost-conscious market.

6.3 Broadcast Television and 4K Ultra HD

The transition to 4K Ultra High Definition (UHD) has revolutionized the broadcast television industry, requiring substantial system bandwidth to handle the increased data flow. The Ariya-10 FPGAs and SOCs provide unparalleled performance and bandwidth capabilities to cater to the transmission needs of 4K UHD broadcasting.

6.4 Military Applications and Signal Bandwidth

The military sector relies heavily on secure communications and radar applications with expanding signal bandwidth requirements. The Ariya-10 FPGAs and SOCs offer the necessary performance and integration capabilities to meet the demands of military applications, even in mobile scenarios.

📈 Quantifying the Performance and Power Requirements of These Applications

The reinvented mid-range FPGAs and SOCs, namely the Ariya-10 series, deliver an impressive 15% higher performance than previous generation high-end FPGAs, coupled with a remarkable 40% lower power consumption compared to their predecessors. Integrating 28 gig transceivers capable of providing 3.6 terabytes per second bandwidth and accommodating over 1 million logic elements, the Ariya-10 series sets new standards in terms of performance, power optimization, and integration capabilities.

🏁 The Path to the New Definition of Mid-Range FPGAs and SOCs

Altera's commitment to innovation and the reinvention of mid-range FPGAs and SOCs is exemplified by the availability of development kits and FPGAs today. The path to embracing this new definition of mid-range starts now, with Altera providing the necessary tools, kits, and FPGAs for designers. Whether power optimization is paramount or maximum performance is critical, designers can initiate their designs today using the Ariya-5 FPGAs or Stratix 5 FPGAs and later transition seamlessly to the Ariya-10 FPGA and SOCs as the silicon becomes available.

🎯 Conclusion

The reinvention of mid-range FPGAs and SOCs by Altera represents a significant breakthrough in the field of FPGA technology. The Ariya-10 series offers unprecedented performance improvements, increased I/O bandwidth, power optimization, and integration capabilities. With software tools that enhance efficiency and productivity, Altera empowers FPGA designers to harness the full potential of these reinvented devices. The diverse range of industries, from telecommunications to storage, broadcast television, and military applications, can now benefit from the breakthrough capabilities of the Ariya-10 FPGAs and SOCs. Embrace the reinvented mid-range, and propel your designs to new heights.

References

• Altera Corporation: https://www.altera.com
• TSMC: https://www.tsmc.com