The History of Intel's i960: A RISC-based Microprocessor

The History of Intel's i960: A RISC-based Microprocessor

Table of Contents

1. Origin
2. Architecture
3. i960 Variants
   1. 80960MX, 80960MC
   2. 80960KA, 80960KB
   3. 80960CA, 80960CF
   4. 80960Jx
   5. 80960VH
4. End of Development
5. Current Status

Intel's i960: A RISC-based microprocessor for embedded systems

Origin

The i960 microprocessor was developed by Intel as a response to the failure of their previous iAPX 432 design. The iAPX 432, which aimed to support high-level languages such as Ada and Lisp, had multiple design flaws and was slower than other processors of its time. In 1984, Intel and Siemens started the BiiN project to create a fault-tolerant computer system using Ada. The i960 was designed as part of this project, incorporating features to improve performance and reliability.

Architecture

To address the performance issues of the iAPX 432, the i960 was designed as a Reduced Instruction Set Computing (RISC) architecture. It featured a 32-bit flat memory space without segmentation and implemented register windows for efficient subroutine calls. The i960 also anticipated a superscalar implementation, allowing for simultaneous execution of multiple instructions.

i960 Variants

80960MX, 80960MC

The i960MX was a full version of the i960, but it was only released for military applications. Its counterpart, the i960MC, was used in high-end embedded systems without mentioning the additional features inherited from the BiiN project.

80960KA, 80960KB

The i960KA was a version of the RISC core without memory management or a Floating-Point Unit (FPU). The i960KB, on the other HAND, combined the RISC core with an FPU. Although these versions were internally identical, they were labeled differently, resulting in larger and more expensive CPUs.

80960CA, 80960CF

The i960CA, announced in 1989, was the first pure RISC implementation of the i960 architecture. It featured a superscalar RISC core and an addressable on-chip cache, making it suitable for high-performance embedded applications. The i960CF, released later, had a larger instruction cache and added a data cache but lacked an FPU or MMU.

80960Jx

The 80960Jx processor was designed specifically for embedded applications. It featured a 32-bit multiplexed address/data bus, instruction, and data cache, on-chip RAM, interrupt controller, and timers. Testability features like ONCE mode and boundary scan were also included.

80960VH

The 80960VH Embedded-PCI processor, announced in 1998, featured a 32-bit PCI bus and a 100 MHz i960JT processor core. It included cache memory, timers, interrupt controller, and DMA controller. This variant was widely used in SCSI disk-array host adapters and some Fibre Channel switches.

End of Development

Intel's attempt to position the i960 in the I/O device controller market with the I2O standard was largely unsuccessful, leading to the end of its development. By the mid-1990s, the i960 faced competition from more recent processors, and Intel did not produce a low-power version suitable for battery-powered systems. The i960 project team shifted their focus to the development of the P6 processor, which later became the Pentium Pro.

Current Status

Despite its decline in the general computing market, the i960 processor family continues to be used in various applications. It is commonly found in high-end SCSI controllers, RAID controllers, and slot machines. The i960 is also utilized in the Indian Air Force's HAL Tejas aircraft and the Indian Space Research Organisation's launch vehicles. Moreover, it is used in radar plotting aid boards and some HP X-Terminals.