Creating and Simulating a Maxc Intel FPGA IP Example Design

Table of Contents

1. Introduction
2. Background Information on Maxic IP
3. IP Block Diagram
4. Creating the Example Design using Quartus Prime
5. Configuring the Maxsec IP
6. Generating the Example Design
7. Simulating the Design using Quest the Sim
8. Analyzing the Simulated Waveforms
9. Conclusion
10. Resources

Introduction

In this article, we will explore the process of creating and simulating a Maxc Intel FPGA IP example design targeted for an Intel agilex 7 FPGA. We will use Quartus Prime Pro software version 22.4 and Quest the Sim revision 2022.10 for this demonstration. Additionally, we will provide a brief overview of the Maxic IP and its block diagram to provide context for the example design. So, let's dive in and learn how to create and simulate a Maxc Intel FPGA IP example design step by step.

Background Information on Maxic IP

Before we delve into the example design, let's understand the significance of the Maxic IP. The Maxic IP provides data confidentiality and integrity for the Ethernet protocol by adding a small overhead at the data link layer. It enables high-speed and low-latency security, making it ideal for securing data between the cloud and data centers, 5G networks, and secure IoT devices on the LAN. The Maxic IP is a highly parameterizable block that uses standard interfaces such as AXI-ST and AXI-Lite to connect to other Intel FPGA IPs.

Pros:

• Provides data confidentiality and integrity for the Ethernet protocol.
• Enables high-speed and low-latency security.
• Widely applicable in various industries including cloud computing, data centers, 5G networks, and IoT devices.

Cons:

• Requires customization and configuration to suit specific requirements.
• Limited to Intel FPGA platforms.

IP Block Diagram

To better understand the example design we are creating, let's review the IP block diagram. The block diagram outlines the flow of data within the example design. It consists of several key components that work together to provide encryption and decryption capabilities.

ADD DIAGRAM DESCRIPTION HERE (based on the provided block diagram)

Creating the Example Design using Quartus Prime

To begin with, we will open Quartus Prime version 22.4 and search for the Maxsec Intel FPGA IP in the IP catalog. Once we locate the Maxsec IP, we will proceed to create an IP file for the Maxsec IP variant, which we will name "demo.ip". The IP file allows us to customize the design according to our specific requirements. We will explore various settings and options available in Quartus Prime to configure the example design.

Configuring the Maxsec IP

Within the Maxsec IP, there are several important settings that we can customize. These settings include the control port, the number of TX and RX ports, the data width, and various encryption and decryption options. We can also adjust parameters for the 802.1 AE Max security standard, such as VLAN tag encryption, frame validation, frame protection, replay protection, and XPN mode. Moreover, there are optional settings for enabling statistics counters and selecting the operation mode for the AXI-ST controlled or common port.

Generating the Example Design

Once we have configured the Maxsec IP, we can proceed to generate the example design. The example designs tab in Quartus Prime allows us to specify The Simulation and synthesis settings for the example design. We can choose to generate simulation file sets and/or synthesis file sets based on our needs. Additionally, we can select the HDL format and development kit for the example design. By specifying the appropriate settings, we can generate the example design files required for simulation and synthesis.

Simulating the Design using Quest the Sim

To verify the functionality of the example design, we will simulate it using Quest the Sim 2022.10. This requires running the simulation scripts provided by Quartus Prime. We can choose from the available simulation run scripts based on the simulator we are using. In this case, we will use the 'vsim -do run_vsim.do' command to run the simulation using Quest the Sim. Once the simulation is complete, we can analyze the simulated waveforms to observe the behavior of the design.

Analyzing the Simulated Waveforms

The simulated waveforms provide valuable insights into the behavior of the example design. We can examine different groups of signals, such as controlled and common, to understand the flow of data within the design. By zooming in on specific sections of the waveforms, we can observe the encryption and decryption processes, data transfer between different components, and the integrity checks performed. This analysis helps in verifying the correct functioning of the example design and enables identification of any issues or anomalies.

Conclusion

In this Tutorial, we have covered the process of creating and simulating a Maxc Intel FPGA IP example design targeted for an Intel agilex 7 FPGA. We began by understanding the background and significance of the Maxc IP, followed by a detailed exploration of the IP block diagram. Using Quartus Prime, we configured the Maxsec IP and generated the example design files. Finally, we simulated the design using Quest the Sim and analyzed the simulated waveforms. This tutorial provides a comprehensive guide to successfully creating and simulating a Maxc Intel FPGA IP example design.

Resources

• Maxsec Intel FPGA IP User Guide: [link]
• Quartus Prime Software Download: [link]
• Intel Agilex FPGA Portfolio: [link]
• Maxic Intel FPGA IP User Guide: [link]